System Control component registers. More...

Detailed Description

System Control component registers.

Definition at line 32 of file cc2538_sys_ctrl.h.

#include <cc2538_sys_ctrl.h>

Data Fields
union {

cc2538_reg_t CLOCK_CTRL
	Clock control register. More...

struct {

cc2538_reg_t SYS_DIV: 3
	System clock rate setting. More...

cc2538_reg_t RESERVED1: 5
	Reserved bits. More...

cc2538_reg_t IO_DIV: 3
	I/O clock rate setting. More...

cc2538_reg_t RESERVED2: 5
	Reserved bits. More...

cc2538_reg_t OSC: 1
	System clock oscillator selection. More...

cc2538_reg_t OSC_PD: 1
	Oscillator power-down. More...

cc2538_reg_t RESERVED3: 3
	Reserved bits. More...

cc2538_reg_t AMP_DET: 1
	Amplitude detector of XOSC during power up. More...

cc2538_reg_t RESERVED4: 2
	Reserved bits. More...

cc2538_reg_t OSC32K: 1
	32-kHz clock oscillator selection More...

cc2538_reg_t OSC32K_CADIS: 1
	Disable calibration 32-kHz RC oscillator. More...

cc2538_reg_t RESERVED5: 6
	Reserved bits. More...

} CLOCK_CTRLbits

}	cc2538_sys_ctrl_clk_ctrl
	Clock control register.

union {

cc2538_reg_t CLOCK_STA
	Clock status register. More...

struct {

cc2538_reg_t SYS_DIV: 3
	Current functional frequency for system clock. More...

cc2538_reg_t RESERVED6: 5
	Reserved bits. More...

cc2538_reg_t IO_DIV: 3
	Current functional frequency for IO_CLK. More...

cc2538_reg_t RESERVED7: 5
	Reserved bits. More...

cc2538_reg_t OSC: 1
	Current clock source selected. More...

cc2538_reg_t OSC_PD: 1
	Oscillator power-down. More...

cc2538_reg_t HSOSC_STB: 1
	HSOSC stable status. More...

cc2538_reg_t XOSC_STB: 1
	XOSC stable status. More...

cc2538_reg_t SOURCE_CHANGE: 1
	System clock source change. More...

cc2538_reg_t RESERVED8: 1
	Reserved bits. More...

cc2538_reg_t RST: 2
	Last source of reset. More...

cc2538_reg_t OSC32K: 1
	Current 32-kHz clock oscillator selected. More...

cc2538_reg_t OSC32K_CALDIS: 1
	Disable calibration 32-kHz RC oscillator. More...

cc2538_reg_t SYNC_32K: 1
	32-kHz clock source synced to undivided system clock (16 or 32 MHz) More...

cc2538_reg_t RESERVED9: 5
	Reserved bits. More...

} CLOCK_STAbits

}	cc2538_sys_ctrl_clk_sta
	Clock status register.

cc2538_reg_t	RCGCGPT
	Module clocks for GPT[3:0] when the CPU is in active (run) mode.

cc2538_reg_t	SCGCGPT
	Module clocks for GPT[3:0] when the CPU is in sleep mode.

cc2538_reg_t	DCGCGPT
	Module clocks for GPT[3:0] when the CPU is in PM0.

cc2538_reg_t	SRGPT
	Reset for GPT[3:0].

cc2538_reg_t	RCGCSSI
	Module clocks for SSI[1:0] when the CPU is in active (run) mode.

cc2538_reg_t	SCGCSSI
	Module clocks for SSI[1:0] when the CPU is insSleep mode.

cc2538_reg_t	DCGCSSI
	Module clocks for SSI[1:0] when the CPU is in PM0.

cc2538_reg_t	SRSSI
	Reset for SSI[1:0].

union {

cc2538_reg_t RCGCUART
	Module clocks for UART[1:0] when the CPU is in active (run) mode. More...

struct {

cc2538_reg_t UART0: 1
	Enable UART0 clock in active (run) mode. More...

cc2538_reg_t UART1: 1
	Enable UART1 clock in active (run) mode. More...

cc2538_reg_t RESERVED: 30
	Reserved bits. More...

} RCGCUARTbits

}	cc2538_sys_ctrl_unnamed1
	UART module clock register - active mode.

union {

cc2538_reg_t SCGCUART
	Module clocks for UART[1:0] when the CPU is in sleep mode. More...

struct {

cc2538_reg_t UART0: 1
	Enable UART0 clock in sleep mode. More...

cc2538_reg_t UART1: 1
	Enable UART1 clock in sleep mode. More...

cc2538_reg_t RESERVED: 30
	Reserved bits. More...

} SCGCUARTbits

}	cc2538_sys_ctrl_unnamed2
	UART module clock register - sleep mode.

union {

cc2538_reg_t DCGCUART
	Module clocks for UART[1:0] when the CPU is in PM0. More...

struct {

cc2538_reg_t UART0: 1
	Enable UART0 clock in PM0. More...

cc2538_reg_t UART1: 1
	Enable UART1 clock in PM0. More...

cc2538_reg_t RESERVED: 30
	Reserved bits. More...

} DCGCUARTbits

}	cc2538_sys_ctrl_unnamed3
	UART module clock register - PM0 mode.

cc2538_reg_t	SRUART
	Reset for UART[1:0].

cc2538_reg_t	RCGCI2C
	Module clocks for I2C when the CPU is in active (run) mode.

cc2538_reg_t	SCGCI2C
	Module clocks for I2C when the CPU is in sleep mode.

cc2538_reg_t	DCGCI2C
	Module clocks for I2C when the CPU is in PM0.

cc2538_reg_t	SRI2C
	Reset for I2C.

cc2538_reg_t	RCGCSEC
	Module clocks for the security module when the CPU is in active (run) mode.

cc2538_reg_t	SCGCSEC
	Module clocks for the security module when the CPU is in sleep mode.

cc2538_reg_t	DCGCSEC
	Module clocks for the security module when the CPU is in PM0.

cc2538_reg_t	SRSEC
	Reset for the security module.

cc2538_reg_t	PMCTL
	Power mode.

cc2538_reg_t	SRCRC
	CRC on state retention.

cc2538_reg_t	RESERVED10 [5]
	Reserved bits.

cc2538_reg_t	PWRDBG
	Power debug register.

cc2538_reg_t	RESERVED11 [2]
	Reserved bits.

cc2538_reg_t	CLD
	This register controls the clock loss detection feature.

cc2538_reg_t	RESERVED12 [4]
	Reserved bits.

cc2538_reg_t	IWE
	This register controls interrupt wake-up.

cc2538_reg_t	I_MAP
	This register selects which interrupt map to be used.

cc2538_reg_t	RESERVED13 [3]
	Reserved bits.

cc2538_reg_t	RCGCRFC
	This register defines the module clocks for RF CORE when the CPU is in active (run) mode.

cc2538_reg_t	SCGCRFC
	This register defines the module clocks for RF CORE when the CPU is in sleep mode.

cc2538_reg_t	DCGCRFC
	This register defines the module clocks for RF CORE when the CPU is in PM0.

cc2538_reg_t	EMUOVR
	This register defines the emulator override controls for power mode and peripheral clock gate.

Field Documentation

◆ AMP_DET

cc2538_reg_t cc2538_sys_ctrl_t::AMP_DET

Amplitude detector of XOSC during power up.

Definition at line 47 of file cc2538_sys_ctrl.h.

◆ CLD

cc2538_reg_t cc2538_sys_ctrl_t::CLD

This register controls the clock loss detection feature.

Definition at line 138 of file cc2538_sys_ctrl.h.

◆ CLOCK_CTRL

cc2538_reg_t cc2538_sys_ctrl_t::CLOCK_CTRL

Clock control register.

Definition at line 38 of file cc2538_sys_ctrl.h.

◆ CLOCK_STA

cc2538_reg_t cc2538_sys_ctrl_t::CLOCK_STA

Clock status register.

Definition at line 59 of file cc2538_sys_ctrl.h.

◆ DCGCGPT

cc2538_reg_t cc2538_sys_ctrl_t::DCGCGPT

Module clocks for GPT[3:0] when the CPU is in PM0.

Definition at line 81 of file cc2538_sys_ctrl.h.

◆ DCGCI2C

cc2538_reg_t cc2538_sys_ctrl_t::DCGCI2C

Module clocks for I2C when the CPU is in PM0.

Definition at line 127 of file cc2538_sys_ctrl.h.

◆ DCGCRFC

cc2538_reg_t cc2538_sys_ctrl_t::DCGCRFC

This register defines the module clocks for RF CORE when the CPU is in PM0.

Definition at line 145 of file cc2538_sys_ctrl.h.

◆ DCGCSEC

cc2538_reg_t cc2538_sys_ctrl_t::DCGCSEC

Module clocks for the security module when the CPU is in PM0.

Definition at line 131 of file cc2538_sys_ctrl.h.

◆ DCGCSSI

cc2538_reg_t cc2538_sys_ctrl_t::DCGCSSI

Module clocks for SSI[1:0] when the CPU is in PM0.

Definition at line 85 of file cc2538_sys_ctrl.h.

◆ DCGCUART

cc2538_reg_t cc2538_sys_ctrl_t::DCGCUART

Module clocks for UART[1:0] when the CPU is in PM0.

Definition at line 116 of file cc2538_sys_ctrl.h.

◆ EMUOVR

cc2538_reg_t cc2538_sys_ctrl_t::EMUOVR

This register defines the emulator override controls for power mode and peripheral clock gate.

Definition at line 146 of file cc2538_sys_ctrl.h.

◆ HSOSC_STB

cc2538_reg_t cc2538_sys_ctrl_t::HSOSC_STB

HSOSC stable status.

Definition at line 67 of file cc2538_sys_ctrl.h.

◆ I_MAP

cc2538_reg_t cc2538_sys_ctrl_t::I_MAP

This register selects which interrupt map to be used.

Definition at line 141 of file cc2538_sys_ctrl.h.

◆ IO_DIV

cc2538_reg_t cc2538_sys_ctrl_t::IO_DIV

I/O clock rate setting.

Current functional frequency for IO_CLK.

Definition at line 42 of file cc2538_sys_ctrl.h.

◆ IWE

cc2538_reg_t cc2538_sys_ctrl_t::IWE

This register controls interrupt wake-up.

Definition at line 140 of file cc2538_sys_ctrl.h.

◆ OSC

cc2538_reg_t cc2538_sys_ctrl_t::OSC

System clock oscillator selection.

Current clock source selected.

Definition at line 44 of file cc2538_sys_ctrl.h.

◆ OSC32K

cc2538_reg_t cc2538_sys_ctrl_t::OSC32K

32-kHz clock oscillator selection

Current 32-kHz clock oscillator selected.

Definition at line 49 of file cc2538_sys_ctrl.h.

◆ OSC32K_CADIS

cc2538_reg_t cc2538_sys_ctrl_t::OSC32K_CADIS

Disable calibration 32-kHz RC oscillator.

Definition at line 50 of file cc2538_sys_ctrl.h.

◆ OSC32K_CALDIS

cc2538_reg_t cc2538_sys_ctrl_t::OSC32K_CALDIS

Disable calibration 32-kHz RC oscillator.

Definition at line 73 of file cc2538_sys_ctrl.h.

◆ OSC_PD

cc2538_reg_t cc2538_sys_ctrl_t::OSC_PD

Oscillator power-down.

Definition at line 45 of file cc2538_sys_ctrl.h.

◆ PMCTL

cc2538_reg_t cc2538_sys_ctrl_t::PMCTL

Power mode.

Definition at line 133 of file cc2538_sys_ctrl.h.

◆ PWRDBG

cc2538_reg_t cc2538_sys_ctrl_t::PWRDBG

Power debug register.

Definition at line 136 of file cc2538_sys_ctrl.h.

◆ RCGCGPT

cc2538_reg_t cc2538_sys_ctrl_t::RCGCGPT

Module clocks for GPT[3:0] when the CPU is in active (run) mode.

Definition at line 79 of file cc2538_sys_ctrl.h.

◆ RCGCI2C

cc2538_reg_t cc2538_sys_ctrl_t::RCGCI2C

Module clocks for I2C when the CPU is in active (run) mode.

Definition at line 125 of file cc2538_sys_ctrl.h.

◆ RCGCRFC

cc2538_reg_t cc2538_sys_ctrl_t::RCGCRFC

This register defines the module clocks for RF CORE when the CPU is in active (run) mode.

Definition at line 143 of file cc2538_sys_ctrl.h.

◆ RCGCSEC

cc2538_reg_t cc2538_sys_ctrl_t::RCGCSEC

Module clocks for the security module when the CPU is in active (run) mode.

Definition at line 129 of file cc2538_sys_ctrl.h.

◆ RCGCSSI

cc2538_reg_t cc2538_sys_ctrl_t::RCGCSSI

Module clocks for SSI[1:0] when the CPU is in active (run) mode.

Definition at line 83 of file cc2538_sys_ctrl.h.

◆ RCGCUART

cc2538_reg_t cc2538_sys_ctrl_t::RCGCUART

Module clocks for UART[1:0] when the CPU is in active (run) mode.

Definition at line 92 of file cc2538_sys_ctrl.h.

◆ RESERVED

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED

Reserved bits.

Definition at line 96 of file cc2538_sys_ctrl.h.

◆ RESERVED1

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED1

Reserved bits.

Definition at line 41 of file cc2538_sys_ctrl.h.

◆ RESERVED10

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED10[5]

Reserved bits.

Definition at line 135 of file cc2538_sys_ctrl.h.

◆ RESERVED11

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED11[2]

Reserved bits.

Definition at line 137 of file cc2538_sys_ctrl.h.

◆ RESERVED12

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED12[4]

Reserved bits.

Definition at line 139 of file cc2538_sys_ctrl.h.

◆ RESERVED13

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED13[3]

Reserved bits.

Definition at line 142 of file cc2538_sys_ctrl.h.

◆ RESERVED2

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED2

Reserved bits.

Definition at line 43 of file cc2538_sys_ctrl.h.

◆ RESERVED3

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED3

Reserved bits.

Definition at line 46 of file cc2538_sys_ctrl.h.

◆ RESERVED4

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED4

Reserved bits.

Definition at line 48 of file cc2538_sys_ctrl.h.

◆ RESERVED5

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED5

Reserved bits.

Definition at line 51 of file cc2538_sys_ctrl.h.

◆ RESERVED6

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED6

Reserved bits.

Definition at line 62 of file cc2538_sys_ctrl.h.

◆ RESERVED7

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED7

Reserved bits.

Definition at line 64 of file cc2538_sys_ctrl.h.

◆ RESERVED8

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED8

Reserved bits.

Definition at line 70 of file cc2538_sys_ctrl.h.

◆ RESERVED9

cc2538_reg_t cc2538_sys_ctrl_t::RESERVED9

Reserved bits.

Definition at line 75 of file cc2538_sys_ctrl.h.

◆ RST

cc2538_reg_t cc2538_sys_ctrl_t::RST

Last source of reset.

Definition at line 71 of file cc2538_sys_ctrl.h.

◆ SCGCGPT

cc2538_reg_t cc2538_sys_ctrl_t::SCGCGPT

Module clocks for GPT[3:0] when the CPU is in sleep mode.

Definition at line 80 of file cc2538_sys_ctrl.h.

◆ SCGCI2C

cc2538_reg_t cc2538_sys_ctrl_t::SCGCI2C

Module clocks for I2C when the CPU is in sleep mode.

Definition at line 126 of file cc2538_sys_ctrl.h.

◆ SCGCRFC

cc2538_reg_t cc2538_sys_ctrl_t::SCGCRFC

This register defines the module clocks for RF CORE when the CPU is in sleep mode.

Definition at line 144 of file cc2538_sys_ctrl.h.

◆ SCGCSEC

cc2538_reg_t cc2538_sys_ctrl_t::SCGCSEC

Module clocks for the security module when the CPU is in sleep mode.

Definition at line 130 of file cc2538_sys_ctrl.h.

◆ SCGCSSI

cc2538_reg_t cc2538_sys_ctrl_t::SCGCSSI

Module clocks for SSI[1:0] when the CPU is insSleep mode.

Definition at line 84 of file cc2538_sys_ctrl.h.

◆ SCGCUART

cc2538_reg_t cc2538_sys_ctrl_t::SCGCUART

Module clocks for UART[1:0] when the CPU is in sleep mode.

Definition at line 104 of file cc2538_sys_ctrl.h.

◆ SOURCE_CHANGE

cc2538_reg_t cc2538_sys_ctrl_t::SOURCE_CHANGE

System clock source change.

Definition at line 69 of file cc2538_sys_ctrl.h.

◆ SRCRC

cc2538_reg_t cc2538_sys_ctrl_t::SRCRC

CRC on state retention.

Definition at line 134 of file cc2538_sys_ctrl.h.

◆ SRGPT

cc2538_reg_t cc2538_sys_ctrl_t::SRGPT

Reset for GPT[3:0].

Definition at line 82 of file cc2538_sys_ctrl.h.

◆ SRI2C

cc2538_reg_t cc2538_sys_ctrl_t::SRI2C

Reset for I2C.

Definition at line 128 of file cc2538_sys_ctrl.h.

◆ SRSEC

cc2538_reg_t cc2538_sys_ctrl_t::SRSEC

Reset for the security module.

Definition at line 132 of file cc2538_sys_ctrl.h.

◆ SRSSI

cc2538_reg_t cc2538_sys_ctrl_t::SRSSI

Reset for SSI[1:0].

Definition at line 86 of file cc2538_sys_ctrl.h.

◆ SRUART

cc2538_reg_t cc2538_sys_ctrl_t::SRUART

Reset for UART[1:0].

Definition at line 124 of file cc2538_sys_ctrl.h.

◆ SYNC_32K

cc2538_reg_t cc2538_sys_ctrl_t::SYNC_32K

32-kHz clock source synced to undivided system clock (16 or 32 MHz)

Definition at line 74 of file cc2538_sys_ctrl.h.

◆ SYS_DIV

cc2538_reg_t cc2538_sys_ctrl_t::SYS_DIV

System clock rate setting.

Current functional frequency for system clock.

Definition at line 40 of file cc2538_sys_ctrl.h.

◆ UART0

cc2538_reg_t cc2538_sys_ctrl_t::UART0

Enable UART0 clock in active (run) mode.

Enable UART0 clock in PM0.

Enable UART0 clock in sleep mode.

Definition at line 94 of file cc2538_sys_ctrl.h.

◆ UART1

cc2538_reg_t cc2538_sys_ctrl_t::UART1

Enable UART1 clock in active (run) mode.

Enable UART1 clock in PM0.

Enable UART1 clock in sleep mode.

Definition at line 95 of file cc2538_sys_ctrl.h.

◆ XOSC_STB

cc2538_reg_t cc2538_sys_ctrl_t::XOSC_STB

XOSC stable status.

Definition at line 68 of file cc2538_sys_ctrl.h.

The documentation for this struct was generated from the following file:

cpu/cc2538/include/cc2538_sys_ctrl.h

Detailed Description

Data Fields

Field Documentation

◆ AMP_DET

◆ CLD

◆ CLOCK_CTRL

◆ CLOCK_STA

◆ DCGCGPT

◆ DCGCI2C

◆ DCGCRFC

◆ DCGCSEC

◆ DCGCSSI

◆ DCGCUART

◆ EMUOVR

◆ HSOSC_STB

◆ I_MAP

◆ IO_DIV

◆ IWE

◆ OSC

◆ OSC32K

◆ OSC32K_CADIS

◆ OSC32K_CALDIS

◆ OSC_PD

◆ PMCTL

◆ PWRDBG

◆ RCGCGPT

◆ RCGCI2C

◆ RCGCRFC

◆ RCGCSEC

◆ RCGCSSI

◆ RCGCUART

◆ RESERVED

◆ RESERVED1

◆ RESERVED10

◆ RESERVED11

◆ RESERVED12

◆ RESERVED13

◆ RESERVED2

◆ RESERVED3

◆ RESERVED4

◆ RESERVED5

◆ RESERVED6

◆ RESERVED7

◆ RESERVED8

◆ RESERVED9

◆ RST

◆ SCGCGPT

◆ SCGCI2C

◆ SCGCRFC

◆ SCGCSEC

◆ SCGCSSI

◆ SCGCUART

◆ SOURCE_CHANGE

◆ SRCRC

◆ SRGPT

◆ SRI2C

◆ SRSEC

◆ SRSSI

◆ SRUART

◆ SYNC_32K

◆ SYS_DIV

◆ UART0

◆ UART1

◆ XOSC_STB