SeeedStudio GD32 RISC-V board

Support for the SeeedStudio GD32 RISC-V board. More...

Detailed Description

Support for the SeeedStudio GD32 RISC-V board.

Author
Koen Zandberg koen@.nosp@m.berg.nosp@m.zand..nosp@m.net
Gunar Schorcht gunar.nosp@m.@sch.nosp@m.orcht.nosp@m..net

Overview

The Seedstudio GD32 RISC-V Dev Board is a development board for the GigaDevice GD32VF103VBT6 MCU with the following on-board components:

Seeedstudio GD32 RISC-V Dev Board

Hardware:

MCU GD32VF103VBT6 Supported
Family RISC-V with ECLIC
Vendor GigaDevice
RAM 32 kByte
Flash 128 KByte
Frequency 108 MHz
Power Modes 3 (Sleep, Deep Sleep, Standby) no
GPIOs 80 yes
Timers 5 x 16-bit timer yes
RTC 1 x 32-bit counter, 20-bit prescaler yes
WDT 2 x 12-bit counter, 3-bit prescaler yes
ADC 2 x 12-bit units, 16 channels @ 1 Msps yes
DAC 2 x 12-bit channel no
UART 2 yes
USART 3 yes
SPI 3 yes
I2C 2 x Fast Mode 400 kHz yes
I2S 2 no
CAN 2 x CAN 2.0B with up to 1 Mbps no
PWM 6 Channels yes
USB 1 x USB FS OTG no
Vcc 3.0V - 3.6V
Datasheet Datasheet
Reference Manual Reference Manual
Board Manual Board Manual
Board Schematic Board Schematic

Pin Layout / Configuration

The general pin layout is shown below.

Seeedstudio GD32 RISC-V Dev Board Pinout

The following table shows the connection of the on-board components with the MCU pins and their configuration in RIOT.

MCU Pin MCU Peripheral RIOT Peripheral Board Function Remark
PA0 BOOT0 BTN0 KEY1
PA1 ADC01_IN1 ADC_LINE(0)
PA2 ADC01_IN2 ADC_LINE(1)
PA3 ADC01_IN3 ADC_LINE(2)
PA9 USART0 TX UART_DEV(0) TX UART TX
PA10 USART0 RX UART_DEV(0) RX UART RX
PA4 SPI1 CS SPI_DEV(1) CS
PA5 SPI1 SCLK SPI_DEV(1) SCLK
PA6 SPI1 MISO SPI_DEV(1) MISO
PA7 SPI1 MOSI SPI_DEV(1) MOSI
PB0 PWM_DEV(0) CH0 LED1 green
PB1 PWM_DEV(0) CH1 LED2 blue
PB5 LED0 red
PB6 I2C0 SCL I2C_DEV(0) SCL
PB7 I2C0 SDA I2C_DEV(0) SDA
PB8 PWM_DEV(1) CH0 N/A if CAN is used
PB9 PWM_DEV(1) CH1 N/A if CAN is used
PB10 I2C1 SCL I2C_DEV(1) SCL
PB11 I2C1 SDA I2C_DEV(1) SDA
PB12 SPI0 CS SPI_DEV(0) CS
PB13 SPI0 SCLK SPI_DEV(0) SCLK
PB14 SPI0 MISO SPI_DEV(0) MISO
PB15 SPI0 MOSI SPI_DEV(0) MOSI
PC0 ADC01_IN10 ADC_LINE(3)
PC1 ADC01_IN11 ADC_LINE(4)
PC2 ADC01_IN12 ADC_LINE(5)
PC3 ADC01_IN13 ADC_LINE(6)
PC4 ADC01_IN14 ADC_LINE(7)
PC5 ADC01_IN15 ADC_LINE(8)
PC13 BTN1 KEY2
- ADC01_IN16 ADC_LINE(9) internal Temperature channel
- ADC01_IN17 ADC_LINE(10) internal VFEF channel

Flashing the Device

The board is flashed via a JTAG interface with OpenOCD (at least release version 0.12.0). By default, an FTDI adapter according to the configuration defined in interface/openocd-usb.cfg is assumed.

BOARD=seeedstudio-gd32 make -C examples/hello-world flash

To use an FTDI adapter with a different configuration, the configuration can be defined using the variable OPENOCD_FTDI_ADAPTER, for example:

OPENOCD_FTDI_ADAPTER=tigar BOARD=seeedstudio-gd32 make -C examples/hello-world flash

If another adapter is used, it can be specified using variable OPENOCD_DEBUG_ADAPTER, for example for a Segger J-Link adapter:

OPENOCD_DEBUG_ADAPTER=jlink BOARD=seeedstudio-gd32 make -C examples/hello-world flash

Accessing STDIO via UART

The stdio is directly accessible through the first UART interface. If an external USB-to-UART interface is used, this interface is mapped to /dev/ttyUSB<n> on a Linux host, where <n> is the index of the UART interface, which is 0 by default.

Use the term target to connect to the board using /dev/ttyUSB0:

BOARD=seeedstudio-gd32 make -C examples/hello-world term

If the UART interface index of board's USB to UART bridge is not 0, use the following command to connect:

BOARD=seeedstudio-gd32 make -C examples/hello-world term PORT=/dev/ttyUSB<n>

Files

file  board.h
 Board specific definitions for the SeeedStudio GD32 RISC-V board.
 
file  gpio_params.h
 Configuration of SAUL mapped GPIO pins.
 
file  periph_conf.h
 Board specific definitions for the SeeedStudio GD32 RISC-V board.