Default clock configuration for SODAQ boards. More...

Detailed Description

Default clock configuration for SODAQ boards.

#include <stdint.h>
#include "cpu.h"
#include "periph_cpu.h"

Include dependency graph for cfg_clock_default.h:

External oscillator and clock configuration
For selection of the used CORECLOCK, we have implemented two choices: usage of the PLL fed by the internal 8MHz oscillator divided by 8 usage of the internal 8MHz oscillator directly, divided by N if needed The PLL option allows for the usage of a wider frequency range and a more stable clock with less jitter. This is why we use this option as default. The target frequency is computed from the PLL multiplier and the PLL divisor. Use the following formula to compute your values: CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL frequency is 96MHz. So PLL_MULL must be between 31 and 95! The internal Oscillator used directly can lead to a slightly better power efficiency to the cost of a less stable clock. Use this option when you know what you are doing! The actual core frequency is adjusted as follows: CORECLOCK = 8MHz / DIV NOTE: A core clock frequency below 1MHz is not recommended
#define	CLOCK_USE_PLL (1)

#define	CLOCK_DIV (1U)

#define	CLOCK_CORECLOCK (8000000 / CLOCK_DIV)

Macro Definition Documentation

#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)

Definition at line 74 of file cfg_clock_default.h.

#define CLOCK_DIV (1U)

Definition at line 72 of file cfg_clock_default.h.

#define CLOCK_USE_PLL (1)

Definition at line 62 of file cfg_clock_default.h.