MSP430 x1xx UART configuration, CPU level. More...
MSP430 x1xx UART configuration, CPU level.
The MSP430 x1xx has two USART peripherals which both can be operated in UART mode. Each is connected to a fixed GPIO for RXD and TXD, respectively. Hence, there is not much left for the board to configure anyway, so we just prepare UART configurations at CPU level for the board to refer to. The unused configuration(s) will be garbage collected by the linker.
Definition at line 143 of file periph_cpu.h.
#include <periph_cpu.h>
Data Fields | |
msp430_usart_params_t | usart_params |
The USART params. | |
uint8_t | tx_enable_mask |
The bitmask to write to the SFR register to enable the USART device in UART mode with TX enabled. | |
uint8_t | rxtx_enable_mask |
The bitmask to write to the SFR register to enable the USART device in UART mode with RX+TX enabled. | |
gpio_t | rxd |
RXD pin. | |
gpio_t | txd |
TXD pin. | |
gpio_t msp430_usart_uart_params_t::rxd |
RXD pin.
Definition at line 164 of file periph_cpu.h.
uint8_t msp430_usart_uart_params_t::rxtx_enable_mask |
The bitmask to write to the SFR register to enable the USART device in UART mode with RX+TX enabled.
The RX and TX part of the UART can be enabled individually. But since there is no way to enable only RX with RIOT's UART API and this is an internal structure anyway, we optimize this to avoid an OR function to compile tx_enable_mask
and rx_enable_mask
.
Definition at line 163 of file periph_cpu.h.
uint8_t msp430_usart_uart_params_t::tx_enable_mask |
The bitmask to write to the SFR register to enable the USART device in UART mode with TX enabled.
Definition at line 152 of file periph_cpu.h.
gpio_t msp430_usart_uart_params_t::txd |
TXD pin.
Definition at line 165 of file periph_cpu.h.
msp430_usart_params_t msp430_usart_uart_params_t::usart_params |
The USART params.
Definition at line 144 of file periph_cpu.h.